1. Field of the Invention
The present invention relates to a method of forming a wiring layer of a semiconductor device and, more particularly, to a method of manufacturing a semiconductor device having a buried electrode structure.
2. Description of the Prior Art
The packing density of semiconductor devices has been increasing recently due to micropatterning. High packing density can be achieved by, for example, micropatterning of a contact hole. The most advanced technique for forming a very small contact hole is reactive ion etching (RIE). A very small contact hole having a very steep wall surface can be obtained by this method. When a very small contact hole with a very steep wall surface is formed by RIE, an electrode layer cannot be properly connected to a semiconductor region formed in a semiconductor substrate by simply depositing an electrode material through this contact hole.
In order to form an electrode layer which is electrically connected to the semiconductor region formed in the substrate through a contact hole formed in an insulating film on the substrate, an electrode material is deposited while the semiconductor substrate is heated. When the substrate is heated, surface diffusion of an electrode material such as aluminum is accelerated, so that the electrode material completely fills the contact hole to achieve good electrical connection between the semiconductor region and the electrode layer.
In the electrode layer forming technique using heating of the substrate, as described above, when the contact hole has a relatively large size of about 3 .mu.m, step coverage in the contact hole is good, so that the electrode material can be properly deposited on the semiconductor region through this contact hole. However, when the size of the contact hole is decreased to 2 .mu.m or less, step coverage in the contact hole becomes poor, even if the substrate is heated. In particular, when the size of the contact hole is decreased to 1 .mu.m or less, the electrode layer will not be electrically connected to the semiconductor region.
In addition, when an aluminum-based metallic material is used as the electrode material, silicon diffuses into the aluminum during annealing, which is performed to achieve good ohmic contact between the electrode material and substrate silicon in the contact hole. When silicon diffuses as described above, a pit is formed in the silicon layer. Aluminum is spiked in the pit. In a planar semiconductor device having a shallow p-n junction depth, the pit may reach the junction. As a result, the breakdown voltage of the p-n junction is decreased, and the reverse leakage current is increased, resulting in inconvenience.
In order to overcome these drawbacks, a method is disclosed in Japanese Patent Disclosure (Kokoku) No. 51-147981, wherein polycrystalline silicon is deposited to cover the entire surface of an insulating layer including a contact hole, after the contact hole is formed in the insulating layer, and aluminum as an electrode material is deposited on the polycrystalline silicon layer and is patterned to obtain a desired wiring pattern. Since the polycrystalline silicon is present under the entire area of the aluminum layer in this method, only part of the polycrystalline silicon layer is diffused into the aluminum layer when annealing is performed to achieve good ohmic contact. Therefore, only part of a contact portion between the polycrystalline silicon layer and the aluminum layer is alloyed. However, in the final electrode/wiring structure, most of the electrical connection of the structure with the substrate is achieved by polycrystalline silicon layer, so the contact resistance cannot be decreased, resulting in inconvenience. The decrease in electrical resistance of polycrystalline silicon is limited even if an impurity is doped at a high dose. The electrical resistance of polycrystalline silicon cannot be decreased like that of a metal. In this prior art, an impurity having the same conductivity type as that of the impurity doped in the semiconductor region, is doped in the polycrystalline silicon layer to assure electrical connection between the electrode/wiring layer and the semiconductor region, even if the contact hole is misaligned with respect to the semiconductor region. However, according to this method, as the impurity having a conductivity type determined by that of the semiconductor region is doped in the polycrystalline silicon layer, this conventional method cannot be used in the manufacture of a CMOSFET IC having p- and n-channel transistors.